1. Field of the Invention
The present invention relates to a semiconductor memory device having an address transition detector in which a transition point of a plurality of row addresses or column addresses is detected to generate an internal initialization signal to thereby increase an operation speed of a SRAM (static random access memory), for example. More particularly, this invention relates to a circuit technology for enabling the SRAM to operate at high speed by using a pulse generating circuit capable of varying a pulse width of the internal initialization signal with ease and which can generate a pulse of a constant pulse width, a pulse width enlarging circuit capable of enlarging a pulse width to a desired pulse width and a pulse width sum generating circuit for calculating output signals of a plurality of pulse generating circuits or a plurality of pulse sum generating circuits in an OR fashion.
2. Description of the Prior Art
So far there is known a technology that can reduce an access time of SRAM, for example, by using an ATD (address transition detector).
As shown in FIG. 1 of the accompanying drawings, the ATD circuit includes a plurality of input terminals .phi..sub.1, .phi..sub.2, . . . , .phi..sub.n to which row addresses, for example, are input and exclusive-OR circuits XOR.sub.1, XOR.sub.2, . . . , XOR.sub.n connected correspondingly to the input terminals .phi..sub.1, .phi..sub.2, . . . , .phi..sub.n. The exclusive-OR circuits XOR.sub.1, XOR.sub.2, . . . , XOR.sub.n are respectively supplied with delay address signals S.sub.Sa1, S.sub.Sa2, . . . , S.sub.San from the corresponding input terminals .phi..sub.1, .phi..sub.2, . . . , .phi..sub.n and delay address signals dS.sub.a1, dS.sub.a2, . . . , d.sub.San which result from processing the address signals S.sub.a1, S.sub.a2, . . . , S.sub.an by inverter columns of multiple stages (inverters of four stages are connected in the illustrated example), respectively. The respective exclusive-OR circuits XOR.sub.1, XOR.sub.2, . . . XOR.sub.n output reference pulse signals P.sub.a1, P.sub.a2, . . . , P.sub.an of address detection signals which will be described later on. Operation of the ATD circuit will be described with reference to a timing chart forming FIG. 2. When the address signal S.sub.a1 is changed at timing point t.sub.1, the pulse signal P.sub.a1 from the ATD circuit rises at timing point t.sub.1. At timing point t.sub.2 after a delay time T.sub.1 of the inverter column was passed, the pulse signal P.sub.a1 falls in response to the delay address signal dS.sub.a1 and becomes a pulse signal having a predetermined width T.sub.1.
A memory having the above ATD circuit and the peripheral circuit will be described with reference to FIG. 3.
In FIG. 3, reference numeral 101 depicts a general-purpose row decoder, 102 a general purpose column decoder, 103 and 104 a bit line and an inverting bit line, 105 to 105 memory cells, 108 and 109 column decoder coupling transistors, 110 a bit line equalization circuit, 112 an equalization logic circuit, 113 a row address transition detection (ATD) and control circuit (hereinafter simply referred to as a row ATD.multidot.control circuit), 114 a column address transition detection (ATD) and control circuit (hereinafter simply referred to as a column ATD.multidot.control circuit), 116 and 117 data lines and 118 . . . , 118 word lines.
The bit line equalization circuit 110 includes two N-channel transistors 122, 123 and one P-channel transistor 124. The data line equalization circuit 111 includes two N-channel transistors 126, 127 and one P-channel transistor 128. The equalization logic circuit 112 includes four inverters 131 to 134, two N-channel transistors 136, 137 and one P-channel transistor 138.
Each of the memory cells 105 . . . 105 is a conventional SRAM where input thereof are respectively connected to the word lines 118 . . . 118 and complementary outputs are respectively connected to the bit line 103 and the inverting bit line 104, respectively.
Of the decoder coupling transistors 108 and 109, a gate of the transistor 108 is connected to the output of the column decoder 102, one electrode of the source and drain electrodes thereof is connected to the bit line 103 and the other electrode thereof is connected to the data line 116. A gate of the other column decoder coupling transistor 109 is connected to the output of the column decoder 102, one electrode of the source and drain electrodes thereof is connected to the inverting bit line 104 and the other electrode is connected to the data line 117.
Of the two transistors 122 and 123 constructing the bit line equalization circuit 110, a drain electrode of the transistor 122 is connected to the positive voltage source terminal Vcc, a precharge signal Sp generated by the equalization logic circuit 112 is applied to the gate thereof and a source electrode thereof is connected to the bit line 103. A drain electrode of the other N-channel transistor 123 is connected to the positive voltage source terminal Vcc, the precharge signal Sp generated by the equalization logic circuit 112 is applied to a gate thereof and a source electrode thereof is connected to the inverting bit line 104.
One electrode of the source and drain electrodes of the P-channel transistor 124 constructing the bit line equalization circuit 110 together with the above two N-channel transistors 122, 123 is connected to the bit line 103, the other electrode is connected to the inverting bit line 104 and an equalization signal *Sp generated by the equalization logic circuit 112 is applied to a gate thereof.
Of the two N-channel transistors 126 and 127 constructing the data line equalization circuit 111, a drain electrode of the transistor 126 is connected to the positive voltage source terminal Vcc, a source electrode thereof is connected to the data line 116 and the precharge signal Sp from the equalization logic circuit 112 is applied to a gate thereof. A drain electrode of the other N-channel transistor 127 is connected to the positive voltage source terminal Vcc, a source electrode thereof is connected to the data line 117 and the precharge signal Sp from the equalization logic circuit 112 is applied to a gate thereof.
In the P-channel transistor 128 that constructs the data line equalization circuit 11 together with the two N-channel transistors 126, 127, one electrode thereof is connected the data line 116, the other electrode thereof is connected to the data line 117, and the inverted precharge signal *Sp from the equalization logic circuit 112 is applied to a gate thereof.
Of the four inverters 131 to 134 constructing the equalization logic circuit 112, the first inverter 131 is supplied with a row address transition detection signal (hereinafter simply referred to as a row ATD signal) *RX generated from the row ATD.multidot.control circuit 113 and outputs an inverted signal RX. The second inverter 132 connects its input to the output of the first inverter 131 and outputs an equalization signal *SEq.
Transistors constructing the equalization logic circuit 112 will be described below. A source electrode of the first N-channel transistor 136 is grounded, a gate electrode thereof is connected to the output of the inverter and a drain electrode thereof is connected to an input line 139 of the third inverter 133. A gate of the second N-channel transistor 137 is supplied with the equalization signal *Seq from the inverter 132, one of the source and drain electrodes thereof is connected to the input line 139 and the other electrode is connected so as to receive a column address transition detection signal (hereinafter simply referred to as a column ATD signal) *CX generated from the column ATD.multidot.control circuit 114.
A gate of the P-channel transistor 138 is connected to the gate of the N-channel transistor 136, one of the source and drain electrodes is connected to the input line 139 of the inverter 133 and the other electrode is supplied with the column ATD signal *CX from the column ATD.multidot.control circuit 114.
An input of the third inverter 133 is connected to the input line 139 and outputs the precharge signal Sp. An input of the fourth inverter 134 is connected to the output of the inverter 133 and outputs the inverted signal *Sp of the precharge signal Sp.
The row ATD.multidot.control circuit 113 detects the change of an arbitrary row address signal of the row address signals supplied from the row address bus 141. At that time, when the circuit 113 detects no address skew, the circuit 113 outputs a pulse (row ATD signal) *RX of negative polarity having a signal width of 5 to 6 nsec, for example. When there is an address skew, the signal width of the ATD signal is extended more. The row ATD.multidot.control circuit 113 outputs an enable signal RD to the row decoder 101. The enable signal RD of logic "0" represents the disabled state and the enable signal RD of logic "1" represents the enabled state. The row decoder 101 is controlled by the enable signal RD.
In a similar manner, the column ATD.multidot.control circuit 114 detects the change of the column address signal supplied from the column address bus 142 and outputs a pulse of negative polarity (column ATD signal). Also, the circuit 114 controls the column decoder 102 by an enable signal CD.
When being enabled, the row decoder 101 selects one word line from the word lines 118 . . . 118 determined by the row decoder 101. Similarly, when enabled, the column decoder 102 selects transistors determined by the column decoder 102, e.g., transistors 108 and 109 in the illustrated example.
During the equalization operation (when the row ATD signal is at logic "0" ), the enable signal RD goes to logic "0" to set the row decoder 102 in all non-selection state. The reason for this is as follows. When the enable signal RD, for example, goes to logic "1" and any one of the word lines 118 is selected, an unnecessary current is flowed to the memory cell 105 selected by the word line 118 during the equalization period. Accordingly, the enable signal RD is set to logic "0" so the above-mentioned disadvantage can be avoided.
Further, in the transition of the column address (column ATD signal is at logic "0"), it is frequently observed that, when the row address is not changed, the bit lines 103 and the inverting bit line 104 connected to the data lines 116 and 117 are replaced. Consequently, the potentials of the bit line 103 and the inverting bit line 104 are inverted. There is then the risk that a bad influence will be exerted upon the data read-out speed. Accordingly, the enable signal CD is held at logic "0" until the equalization operation of the data lines 116, 117 is ended to thereby set the column decoder 102 in the all non-selection state.
As described above, in the address transition, the ATD signals (pulse signals) *RX and *CX are generated, the bit line 103 and the inverting bit line 104 are equalized, the potentials of the complementary bit line 103 and inverting bit line 104 are made the same and then the memory cells 105 . . . 105 are activated, thereby increasing the read-out speed of the memory.
However, as shown in FIG. 2, when a pulse-shaped signal having a pulse width .DELTA.t shorter than the delay time T.sub.1 is supplied as the address signal S.sub.a1, for example, at timing point.sub.2, two pulse signals having a pulse width .DELTA.t are successively produced at an interval of the delay time T.sub.1.
That is, there are produced a pulse signal which rises at timing point t.sub.2 and falls at timing point t.sub.3 and a pulse signal which rises at timing point t.sub.4 (=t.sub.2 +t.sub.1) and falls at timing point t.sub.5 (=t.sub.4 +.DELTA.t). When the internal circuit of the SRAM is initialized by using these pulse signals, the initialization cannot be carried out with sufficient time and in worst cases, a malfunction occurs.